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24-bit, 625 ksps, 109 db - adc with on-chip buffers, serial interface AD7763 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 analog devices, inc. all rights reserved. features 120 db dynamic range at 78 khz output data rate 109 db dynamic range at 625 khz output data rate 112 db snr at 78 khz output data rate 107 db snr at 625 khz output data rate 625 khz maximum fully filtered output word rate programmable oversampling rate (32 to 256) flexible serial interface fully differential modulator input on-chip differential amplifier for signal buffering low-pass finite impulse response (fir) filter with default or user-programmable coefficients overrange alert bit digital offset and gain correction registers low power and power-down modes synchronization of multiple devices via sync pin i 2 s interface mode applications data acquisition systems vibration analysis instrumentation functional block diagram 05476-001 AD7763 v in+ v in? av dd1 agnd mclk dgnd v drive av dd2 av dd3 av dd4 dv dd decapa r bias decapb mclkgnd sync reset sh2:0 adr2:0 cdiv i 2 s scp scr sdl drdy sco fso sdo sdi fsi control logic i/o offset and gain registers diff multibit - modulator reconstruction v ref+ refgnd fir filter engine programmable decimation buf figure 1. general description the AD7763 high performance, 24-bit, - analog-to-digital converter (adc) combines wide input bandwidth and high speed with the benefits of - conversion, as well as performance of 107 db snr at 625 ksps, making it ideal for high speed data acquisition. a wide dynamic range, combined with significantly reduced antialiasing requirements, simplifies the design process. an integrated buffer to drive the reference, a differential ampli- fier for signal buffering and level shifting, an overrange flag, internal gain and offset registers, and a low-pass, digital fir filter make the AD7763 a compact, highly integrated data acquisition device requiring minimal peripheral component selection. in addition, the device offers programmable decimation rates and a digital fir filter, which can be user- programmed to ensure that its characteristics are tailored for the users application. the AD7763 is ideal for applications demanding high snr without necessitating the design of complex, front- end signal processing. the differential input is sampled at up to 40 msps by an analog modulator. the modulator output is processed by a series of low-pass filters, the final filter having default or user- programmable coefficients. the sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763. the reference voltage supplied to the AD7763 determines the analog input range. with a 4 v reference, the analog input range is 3.2 v differential-biased around a common mode of 2 v. this common-mode biasing can be achieved using the on-chip differential amplifiers, further reducing the external signal conditioning requirements. the AD7763 is available in an exposed paddle, 64-lead tqfp_ep and is specified over the industrial temperature range from ?40c to +85c. table 1. related devices part no. description ad7760 24-bit, 2.5 msps, 100 db -, parallel interface ad7762 24-bit, 625 ksps, 109 db -, parallel interface
AD7763 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 specifications ..................................................................................... 3 timing specifications ....................................................................... 5 timing diagrams .......................................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 ter mi nolo g y .................................................................................... 10 typical performance characteristics ........................................... 11 theory of operation ...................................................................... 14 AD7763 interface ............................................................................ 15 reading data using the spi interface ..................................... 15 synchronization .......................................................................... 15 sharing the serial bus ................................................................ 15 writing to the AD7763 .............................................................. 16 reading status and other registers ......................................... 17 reading data using the i 2 s interface ....................................... 18 clocking the AD7763 ..................................................................... 19 example 1 .................................................................................... 19 example 2 .................................................................................... 19 driving the AD7763 ....................................................................... 20 using the AD7763 ...................................................................... 21 bias resistor selection ............................................................... 21 decoupling and layout recommendations ................................ 22 supply decoupling ..................................................................... 23 additional decoupling .............................................................. 23 reference voltage filtering ....................................................... 23 differential amplifier components ........................................ 23 exposed paddle ........................................................................... 23 layout considerations ............................................................... 23 programmable fir filter ............................................................... 24 downloading a user-defined filter ............................................ 25 example filter download ......................................................... 26 registers ........................................................................................... 27 control register 1address 0x001 ......................................... 27 control register 2address 0x002 ......................................... 27 status register (read only) ...................................................... 28 offset registeraddress 0x003 ............................................... 28 gain registeraddress 0x004 ................................................. 28 overrange registeraddress 0x005 ....................................... 28 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision history 10/05revision 0: initial version
AD7763 rev. 0 | page 3 of 32 specifications av dd1 = dv dd = v drive = 2.5 v; av dd2 = av dd3 = av dd4 = 5 v; v ref = 4.096 v; mclk amplitude = 5 v; t a = 25c; normal mode, using on-chip amplifier with components as shown in tabl e 10 , unless otherwise noted. 1 table 2. parameter test conditions/comments specification unit dynamic performance decimate 256 mclk = 40 mhz, odr = 78 khz, f in = 1 khz dynamic range modulator inputs shorted 119 120.5 db min db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 dbfs 112 db typ input amplitude = ?60 db 59 dbc typ nonharmonic, input amplitude = ?6 db 126 dbc typ spurious-free dynamic range (sfdr) input amplitude = ?60 db 77 dbc typ input amplitude = ?0.5 dbfs ?105 db typ input amplitude = ?6 db ?106 dbc typ total harmonic distortion (thd) input amplitude = ?60 db ?75 dbc typ decimate 64 mclk = 40 mhz, odr = 312.5 khz, f in = 1 khz dynamic range modulator inputs shorted 112 113 db min db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 dbfs 109.5 db typ spurious-free dynamic range (sfdr) nonharmonic, input amplitude = ?6 db 126 dbc typ decimate 32 mclk = 40 mhz, odr = 625 khz, f in = 100 khz dynamic range modulator inputs shorted 108 109.5 db min db typ signal-to-noise ratio (snr) 2 input amplitude = ?0.5 dbfs 107 db typ nonharmonic, input amplitude = ?6 db 120 dbc typ input amplitude = ?0.5 dbfs ?105 db typ spurious-free dynamic range (sfdr) total harmonic distortion (thd) input amplitude = ?6 db ?107 dbc typ dc accuracy resolution 24 bits differential nonlinearity guaranteed monotonic to 24 bits integral nonlinearity 0.00076 % typ 0.014 % typ zero error 0.02 % max gain error 0.018 % typ zero error drift 10 %fs/c typ gain error drift 0.0002 %fs/c typ digital filter response decimate 32 group delay mclk = 40 mhz 47 s typ decimate 64 group delay mclk = 40 mhz 91.5 s typ decimate 256 group delay mclk = 40 mhz 358 s typ analog input differential input voltage v in (+) C v in (?), v ref = 2.5 v 2 v p-p v in (+) C v in (?), v ref = 4.096 v 3.25 v p-p input capacitance at internal buffer inputs 5 pf typ at modulator inputs 55 pf typ
AD7763 rev. 0 | page 4 of 32 parameter test conditions/comments specification unit reference input v ref input voltage v dd3 = 3.3 v 5% +2.5 v max v dd3 = 5 v 5% +4.096 v max v ref input dc leakage current 1 a max v ref input capacitance 5 pf max power dissipation total power dissipation normal power mode 955.5 mw max low power mode 651 mw max standby mode clock stopped 6.35 mw typ power requirements av dd1 (modulator supply) 5% +2.5 v av dd2 (general supply) 5% +5 v av dd3 (differential amplifier supply) +3.15/+5.25 v min/max av dd4 (reference buffer supply) +3.15/+5.25 v min/max dv dd 5% +2.5 v v drive +1.65/+2.7 v min/max normal mode ai dd1 (modulator) 49/52 ma typ/max ai dd2 (general) 40/43 ma typ/max ai dd4 (reference buffer) av dd4 = 5 v 35/37 ma typ/max low power mode ai dd1 (modulator) 26/28 ma typ/max ai dd2 (general) 20/23 ma typ/max ai dd4 (reference buffer) av dd4 = 5 v 10/11 ma typ/max ai dd3 (diff amp) av dd3 = 5 v, both modes 41/45 ma typ/max di dd both modes 56/62 ma typ/max digital i/o mclk input amplitude 3 5 v typ input capacitance 7.3 pf typ input leakage current 1 a/pin max three-state leakage current (sdo) 1 a max v inh 0.7 v drive v min v inl 0.3 v drive v max v oh 4 1.5 v min v ol 0.1 v max 1 see the terminology section. 2 snr specifications in db are referred to a full-scale input, fs, and tested with an input signal at 0.5 db below full scale, u nless otherwise specified. 3 while the AD7763 can function with an mclk amplitude of less than 5 v, this is the re commended amplitude to achieve the perfor mance as stated. 4 tested with a 400 a load current.
AD7763 rev. 0 | page 5 of 32 timing specifications av dd1 = dv dd = v drive = 2.5 v, av dd2 = av dd3 = av dd4 = 5 v, t a = 25c, normal mode, unless otherwise noted. table 3. parameter limit at t min , t max unit description f mclk 1 mhz min applied master clock frequency 40 mhz max f iclk 500 khz min internal modulator clock derived from mclk 20 mhz max t 1 1 1 t iclk or 0.5 t iclk 2 typ sco high period t 2 1 2 1 t iclk or 0.5 t iclk typ sco low period t 3 t sco 3 typ drdy low period t 3a 4 2 ns typ sco rising edge to drdy falling edge t 3b 4 3 ns typ sco rising edge to drdy rising edge t 4 5 32 t sco 3 typ fso low period t 4a 4 , 5 1 ns typ sco rising edge to fso falling edge t 4b 4 , 5 2 ns typ sco falling edge to fso rising edge t 5 6.5 ns max initial data access time t 6 4 5 ns max sco rising edge to sdo valid t 7 0.5 t sco 3 ns min sdo valid after sco falling edge t 8 16 t sco 3 typ drdy rising edge to sdl falling edge t 9 t sco 3 typ sdl pulse width t 10 5.5 ns max sdo three-state to sco rising edge t 11 1 t sco 3 min fsi low period t 12 12 ns min sdi setup time t 13 10 ns min sdi hold time t 14 12 ns min fsi setup time t 15 16 t sco 3 typ sdl falling edge to sdl falling edge 1 t iclk = 1/f iclk . 2 sco frequency selected by scr and cdiv pins. 3 t sco = t 1 + t 2 . 4 all edges mentioned refer to scp = 0. invert sco edges for scp = 1. 5 in decimate 32 mode, this time specification applies only when cdiv = 0 and scr =1. for all other combinations of cdiv and scr in decimate 32 mode, the fso signal is constantly logic low.
AD7763 rev. 0 | page 6 of 32 timing diagrams d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 st6 st5 st4 st3 st2 st1 st0 fso (o) sco (o) drdy (o) sdo (o) sdl (o) t 10 t 4b t 4a t 3 t 3b t 3a t 2 t 5 t 6 t 7 t 9 t 1 t 4 t 8 t 15 05476-002 figure 2. spi? interface serial read timing diagram all adr2 adr1 adr0 ra11 ra10 ra1 ra0 d15 d14 d1 d0 sco (o) fsi (i) sdi (i) 32 t sco t 1 t 14 t 12 t 13 t 2 t 11 05476-003 figure 3. register write serial data from adc a 32 t sco serial data from adc b serial data from adc c serial data from adc d fso b drdy a (o) sco (o) sdo (o) fso c fso d fso a 32 t sco 32 t sco 32 t sco 05476-004 figure 4. spi interface serial read timing with multiple AD7763 devices sharing the serial bus
AD7763 rev. 0 | page 7 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating av dd1 to gnd ?0.3 v to +3 v (av dd2 , av dd3 , av dd4 ) to gnd ?0.3 v to +6 v dv dd to gnd ?0.3 v to +3 v v drive to gnd ?0.3 v to +3 v v in+ , v inC to gnd ?0.3 v to +6 v digital input voltage to gnd 1 ?0.3 v to dv dd + 0.3 v mclk to mclkgnd ?0.3 v to +6 v v ref to gnd 2 ?0.3 v to av dd4 + 0.3 v agnd to dgnd ?0.3 v to +0.3 v input current to any pin except supplies 3 10 ma operating temperature range commercial ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tqfp_ep exposed paddle ja thermal impedance 92.7c/w jc thermal impedance 5.1c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 600 v 1 absolute maximum voltage on digital inputs is 3.0 v or dv dd + 0.3 v, whichever is lower. 2 absolute maximum voltage on v ref input is 6.0 v or av dd4 + 0.3 v, whichever is lower. 3 transient currents of up to 200 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
AD7763 rev. 0 | page 8 of 32 pin configuration and fu nction descriptions 64 dgnd 63 v drive 62 dgnd 61 i 2 s 60 scr 59 dgnd 58 cdiv 57 dgnd 56 fso 55 sco 54 sdo 53 dgnd 52 sdi 51 fsi 50 sdl 49 scp 47 adr1 46 adr2 45 sh0 42 dgnd 43 dgnd 44 v drive 48 adr0 41 dv dd 40 sh1 39 sh2 37 reset 36 sync 35 dgnd 34 agnd1 33 av dd1 38 drdy 2 mclkgnd 3 mclk 4 av dd2 7 agnd1 6 av dd1 5 agnd2 1 dgnd 8 decapa 9 refgnd 10 v ref+ 12 av dd4 13 agnd2 14 av dd2 15 av dd2 16 agnd2 11 agnd4 pin 1 17 r bias 18 agnd2 19 v in a+ 20 v in a? 21 v out a? 22 v out a+ 23 agnd3 24 av dd3 25 v in + 26 v in ? 27 av dd2 28 agnd2 29 agnd3 30 decapb 31 agnd3 32 agnd3 AD7763 top view (not to scale) 05476-005 figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 6, 33 av dd1 power supply for modulator, 2.5 v. these pins sh ould be decoupled to agnd1 with 100 nf and 10 f capacitors on each pin. 4, 14, 15, 27 av dd2 power supply, 5 v. these pins should be decouple d to agnd2 with 100 nf capacitors on each of pin 4, pin 14, and pin 15. pin 27 should be connected to pin 14 via an 8.2 nh inductor. 24 av dd3 power supply for differential amplifier, 3.3 v to 5 v. this pin should be decoupled to agnd3 with a 100 nf capacitor. 12 av dd4 power supply for reference buffer, 3.3 v to 5 v. this pin should be decoupled to agnd4 with a 10 nf capacitor in series with a 10 ? resistor. 7, 34 agnd1 power supply ground for analog circuitry powered by av dd1 . 5, 13, 16, 18, 28 agnd2 power supply ground for analog circuitry powered by av dd2 . 23, 29, 31, 32 agnd3 power supply ground for analog circuitry powered by av dd3 . 11 agnd4 power supply ground for analog circuitry powered by av dd4 . 9 refgnd reference ground. ground connection for the reference voltage. 41 dv dd power supply for digital circuitry and fir filter, 2.5 v. this pin should be decoupled to dgnd with a 100 nf capacitor. 44, 63 v drive logic power supply input, 1.8 v to 2.5 v. the voltage supplied at these pins determines the operating voltage of the logic interface. these pins must be connected together and tied to the same supply. each pin should also be decoupled to dgnd with a 100 nf capacitor. 1, 35, 42, 43, 53, 57, 59, 62, 64 dgnd ground reference for digital circuitry. 19 v in a+ positive input to differential amplifier. 20 v in a? negative input to differential amplifier. 21 v out a? negative output from differential amplifier. 22 v out a+ positive output from differential amplifier. 25 v in + positive input to the modulator. 26 v in ? negative input to the modulator. 10 v ref+ reference input. the input range of this pin is determined by the reference buffer supply voltage (av dd4 ). see the reference voltage filtering section for more details. 8 decapa decoupling pin. a 100 nf capacitor must be inserted between this pin and agnd1. 30 decapb decoupling pin. a 33 pf capacitor mu st be inserted between this pin and agnd3.
AD7763 rev. 0 | page 9 of 32 pin no. mnemonic description 17 r bias bias current setting. a resistor must be inserted between this pin and agnd. see the bias resistor selection section. 37 reset a falling edge on this pin resets all internal digital circuitry. holding this pin low keeps the AD7763 in a reset state. 3 mclk master clock input. a low jitter digital clock must be applied to this pin. the output data rate depends on the frequency of this clock. see the clocking the AD7763 section. 2 mclkgnd master clock ground sensing pin. 36 sync synchronization input. a falling edge on this pin resets the internal filter. this can be used to synchronize multiple devices in a system. 38 drdy data ready output. each time new conversion data is available, an active low pulse, ? iclk period wide, is produced on this pin. see the AD7763 interface section. 39, 40, 45 sh2:0 share pins 2:0. for multiple AD7763 devices sharing a common serial bus. each device is wired with the binary value that represents the number of devices sharing the serial bus. sh2 is the msb. see the sharing the serial bus section. 46 to 48 adr2:0 address 2:0. allows multiple AD7763 devices to shar e a common serial bus. each device must be programmed with an individual address using these three pins. see the sharing the serial bus section. 49 scp serial clock polarity. determines on which edge of sco the data bits are clocked out and on which edge they are valid. all timing diagrams are shown with scp = 0, and all sco edges shown should be inverted for scp = 1. 50 sdl serial data latch. a pulse is output on this pin after every 16 data bits. the pulse is one sco period wide and can be used in conjunction with fso as an alternative framing method for serial transfers requiring a framing sign al more frequent than every 32 bits. 51 fsi frame sync in. the status of this pin is checked on the falling edge of sco. if this pin is low, then the first data bit is latched in on the next sco fa lling edge when scp = 0 or on the rising edge of sco if scp = 1. 52 sdi serial data in. the first data bi t (msb) must be valid on the next sco falling edge when scp = 0 (or sco rising edge scp = 1) after the fsi event has been latched. each write requires 32 bits: the all bit, 3 address bits, and 12 register address bits, followed by the remaining 16 bits of data to be written to the device. 54 sdo serial data out. address, status , and data bits are clocked out on this line during each serial transfer. if scp = 0, each bit is clocked out on an sco ri sing edge and is valid on the falling edge. when the i 2 s pin is set to logic high, this pin outp uts the signal defined as sd in the i 2 s bus specification. see the reading data using the i s interface 2 section for details. 55 sco serial clock out. this clock signal is derived fr om the internal iclk signal. the frequency of sco is equal to either iclk or iclk/2, depending on the state of the cdiv and scr pins (see the AD7763 interface section). when the i 2 s pin is logic high, this pin outputs the signal defined as sck by the i 2 s bus specification. see the reading data using the i s interface 2 section. 56 fso frame sync out. this signal frames the seri al data output and is 32 sco periods wide. the exception to the framing behavior of fso occurs in decimate 32 mode, where, for certain combinations of cdiv and scr, the fso signal is constantly logic low. see the reading data using the spi interface section. when the i 2 s pin is set to logic high, this pin outputs the signal defined as ws in the i 2 s bus specification. see the reading data using the i s interface 2 section. 58 cdiv clock divider. this pin is used to select the ratio of mclk to iclk. see the AD7763 interface section. 60 scr serial clock rate. this pin and the cdiv pin program the sco frequency (see table 7 ). 61 i 2 s i 2 s select. a logic 1 on this pin changes the serial data-out mode from spi to i 2 s. the sdo pin outputs as the sd signal, the sco pin outputs the sck signal, and the fso pin outputs the ws signal. when writing to the AD7763, the i 2 s pin is set to logic low and the spi interface is used. see the reading data using the i s interface 2 section for further details.
AD7763 rev. 0 | page 10 of 32 terminology signal-to-noise ratio (snr) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist fre- quency, excluding harmonics and dc. the value for snr is expressed in decibels. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the AD7763, it is defined as () 1 6 54 32 v vvvvv thd 22222 log20db ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonic. nonharmonic spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, excluding harmonics. dynamic range the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. integral nonlinearity (inl) the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero error the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. zero error drift the change in the actual zero error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature. gain error the first transition (from 100000 to 100001) should occur for an analog voltage 1/2 lsb above the nominal negative full scale. the last transition (from 011110 to 011111) should occur for an analog voltage 1 1/2 lsb below the nominal full scale. the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition, from the diffe rence between the ideal levels. gain error drift the change in the actual gain error value due to a temperature change of 1c. it is expressed as a percentage of full scale at room temperature.
AD7763 rev. 0 | page 11 of 32 typical performance characteristics av dd1 = dv dd = v drive = 2.5 v, av dd2 = av dd3 = av dd4 = 5 v, v ref = 4.096 v, t a = 25c, normal mode, unless otherwise noted. all ffts are generated from 65536 samples using a 7-term blackman-harris window. 0 ?50 ?100 ?150 ?200 ?250 0 5000 15000 10000 30000 35000 25000 20000 05476-007 amplitude (db) frequency (hz) figure 6. normal mode fft, 1 khz, ?0.5 db input tone, 256 decimation 0 ?50 ?100 ?150 ?200 ?250 0 5000 15000 10000 30000 35000 25000 20000 05476-011 amplitude (db) frequency (hz) figure 7. normal mode fft, 1 khz, ?0.6 db input tone, 256 decimation 0 ?50 ?100 ?150 ?200 ?250 0 5000 15000 10000 30000 35000 25000 20000 05476-032 amplitude (db) frequency (hz) figure 8. normal mode fft, 1 khz, ?60 db input tone, 256 decimation 0 ?50 ?100 ?150 ?200 ?250 0 5000 15000 10000 30000 35000 25000 20000 05476-006 amplitude (db) frequency (hz) figure 9. low power fft, 1 khz, ?0.5 db input tone, 256 decimation 0 ?50 ?100 ?150 ?200 ?250 0 5000 15000 10000 30000 35000 25000 20000 05476-010 amplitude (db) frequency (hz) figure 10. low power fft, 1 khz, ?6 db input tone, 256 decimation 0 ?50 ?100 ?150 ?200 ?250 0 5000 15000 10000 30000 35000 25000 20000 05476-031 amplitude (db) frequency (hz) figure 11. low power fft, 1 khz, ?60 db input tone, 256 decimation
AD7763 rev. 0 | page 12 of 32 0 ?50 ?100 ?150 ?200 ?250 0 50000 150000 100000 300000 250000 200000 05476-009 amplitude (db) frequency (hz) figure 12. normal mode fft, 100 khz, ?0.5 db input tone, 32 decimation 0 ?50 ?100 ?150 ?200 ?250 0 50000 150000 100000 300000 250000 200000 05476-030 amplitude (db) frequency (hz) figure 13. normal mode fft, 100 khz, ?6 db input tone, 32 decimation 120 114 116 118 112 110 108 106 06 4 ?6db ?60db ?0.5db 192 128 256 05476-036 snr (dbfs) decimation rate ( ) figure 14. normal mode snr vs. de cimation rate, 1 khz input tone 0 ?50 ?100 ?150 ?200 ?250 0 50000 150000 100000 300000 250000 200000 05476-008 amplitude (db) frequency (hz) figure 15. low power fft, 100 khz, ?0 .5 db input tone, 32 decimation 0 ?50 ?100 ?150 ?200 ?250 0 50000 150000 100000 300000 250000 200000 05476-029 amplitude (db) frequency (hz) figure 16. low power fft, 100 khz, ?6 db input tone , 32 decimation 116 114 112 110 108 106 104 06 4 ?6db ?60db ?0.5db 192 128 256 05476-033 snr (dbfs) decimation rate ( ) figure 17. low power snr vs. deci mation rate, 1 khz input tone
AD7763 rev. 0 | page 13 of 32 4500 1000 500 1500 2000 2500 3000 3500 4000 0 8385341 8385401 8385391 8385381 8385371 8385361 8385351 05476-035 occurence 24-bit code figure 18. normal mode, 24-bit histogram, 256 decimation 0.0010 ?0.0010 0 16777216 05476-037 24-bit code inl (%) 0.0005 0 ?0.0005 4194304 8388608 12582912 +25 c ?40 c +85 c figure 19. 24-bit inl, normal power mode 0.65 ?0.6 0 16777216 05476-039 24-bit code dnl (lsb) 0.2 0.4 0 ?0.2 ?0.4 4194304 8388608 12582912 figure 20. 24-bit dnl 6000 1000 2000 3000 4000 5000 0 8383091 8383191 8383171 8383151 8383131 8383111 05476-034 occurence 24-bit code figure 21. low power 24-bit histogram, 256 decimation 0.0015 ?0.0010 0 16777216 05476-038 24-bit code inl (%) 0.0005 0.0010 0 ?0.0005 4194304 8388608 12582912 +25 c ?40 c +85 c figure 22. 24-bit inl, low power mode
AD7763 rev. 0 | page 14 of 32 theory of operation the AD7763 employs a - conversion technique to convert the analog input into an equivalent digital word. the modulator samples the input waveform and outputs an equivalent digital word to the digital filter at a rate equal to iclk. due to the high oversampling rate, which spreads the quanti- zation noise from 0 to f iclk , the noise energy contained in the band of interest is reduced (see figure 23 ). to further reduce quantization noise, a high order modulator is employed to shape the noise spectrum; thus, most of the noise energy is shifted out of the band of interest (see figure 24 ). the digital filtering that follows the modulator removes the large out-of-band quantization noise (see figure 25 ), while also reducing the data rate from f iclk at the input of the filter to f iclk /32 or less at the output of the filter, depending on the decimation rate used. digital filtering has certain advantages over analog filtering. it does not introduce significant noise or distortion and can be made perfectly linear phase. the AD7763 employs three finite impulse response (fir) filters in series. by using different combinations of decimation ratios and filter selection, data can be obtained from the AD7763 at four different data rates. the first filter receives data from the modulator at iclk mhz, where it is decimated 4 to output data at (iclk/4) mhz . the second filter allows the decimation rate to be chosen from 8 to 32. the third filter has a fixed decimation rate of 2x, is user programmable, and has a default configuration (see the programmable fir filter section). this filter can be bypassed. table 6 shows some characteristics of the default filter. the group delay of the filter is defined as the delay to the center of the impulse response and is equal to the computation plus filter delays. the delay until valid data is available (the dvalid status bit is set) is equal to 2 the filter delay plus the computation delay. 05476-024 quantization noise f iclk /2 band of interest figure 23. - adc, quantization noise 05476-025 f iclk /2 noise shaping band of interest figure 24. - adc, noise shaping 05476-012 f iclk /2 band of interest digital filter cutoff frequency figure 25. - adc, digita l filter cutoff frequency table 6. configuration with default filter icl frequency filter 1 filter 2 filter 3 data state computation delay filter delay pass and andidth output data rate (odr) 20 mhz 4 4 2 fully filtered 1.775 s 44.4 s 250 khz 625 khz 20 mhz 4 8 bypassed partially filtered 2.6 s 10.8 s 140.625 khz 625 khz 20 mhz 4 8 2 fully filtered 2.25 s 87.6 s 125 khz 312.5 khz 20 mhz 4 16 bypassed partially filtered 4.175 s 20.4 s 70.3125 khz 312.5 khz 20 mhz 4 16 2 fully filtered 3.1 s 174 s 62.5 khz 156.25 khz 20 mhz 4 32 bypassed partially filtered 7.325 s 39.6 s 35.156 khz 156.25 khz 20 mhz 4 32 2 fully filtered 4.65 s 346.8 s 31.25 khz 78.125 khz 12.288 mhz 4 8 2 fully filtered 3.66 s 142.6 s 76.8 khz 192 khz 12.288 mhz 4 16 2 fully filtered 5.05 s 283.2 s 38.4 khz 96 khz 12.288 mhz 4 32 bypassed partially filtered 11.92 s 64.45 s 21.6 khz 96 khz 12.288 mhz 4 32 2 fully filtered 7.57 s 564.5 s 19.2 khz 48 khz
AD7763 rev. 0 | page 15 of 32 AD7763 interface reading data using the spi interface the timing diagram in figure 2 shows how the AD7763 transmits its conversion results using the spi-compatible serial interface. the data being read from the AD7763 is clocked out using the serial clock output, sco. the sco frequency is dependent on the state of the serial clock output rate pin, scr, and the clock divider mode chosen by the state of the clock divider pin, cdiv (see the clocking the AD7763 section). tabl e 7 shows both the sco frequency and the iclk frequency for the AD7763, resulting from the states of both the cdiv and scr pins. table 7. sco frequency clock divide mode cdiv scr sco frequency iclk frequency divide by 1 1 0 mclk mclk 1 mclk mclk divide by 2 0 0 mclk/2 mclk/2 1 mclk 1 mclk/2 1 in decimate 32 mode, when cdiv = 0 and scr = 1, fso pulses low for 32 sco clock cycles, as shown in figure 2 . for all other combinations of cdiv and scr in decimate 32 mode, fso is continuously low. an active low pulse of one sco period on the data-ready output, drdy , indicates a new conversion result is available at the AD7763 serial data output, sdo. each bit of the new conversion result is clocked onto the sdo line on the rising sco edge and is valid on the falling sco edge (for scp = 0). the conversion result spans 32 sco clock cycles and consists of 24 data bits in twos complement form, followed by 7 status bits. d6 d5 d4 d3 d2 d1 d0 adr2 adr1 adr0 dvalid ovr lpwr filter_ok the conversion result output on the sdo line is framed by the frame synchronization output, fso , which is sent logic low for 32 sco cycles following the rising edge of the drdy signal. note that the sdo line is in three-state for one clock cycle before the fso signal returns to logic high, which means that only 31 actual data bits are output in each conversion. the first three status bits, adr[2:0], are the device address bits. the dvalid bit is asserted when the data being clocked out on the sdo line is valid. table 19 contains descriptions of the other status bits: ovr, lpwr, and filter_ok. there is an exception to the behavior of fso when the AD7763 operates in decimate 32 mode (see endnote 1 of table 7 ). if scr and cdiv are chosen so that the sco frequency output has the capability to clock through only 32 sco cycles before the msb of the next conversion result is output, then fso stays logic low continuously. the AD7763 also features a serial data latch output, sdl, which outputs a pulse every 16 data bits. the sdl output offers an alternative framing signal for serial transfers, which require a framing signal more frequent than every 32 bits. synchronization the sync input to the AD7763 provides a synchronization function that allows the user to begin gathering samples of the analog front-end input from a known point in time. the sync function allows multiple AD7763s, operated from the same master clock and using the same sync signal, to be synchronized so that each adc simultaneously updates its output register. using a common sync signal to all AD7763 devices in a system allows synchronization to occur. on the falling edge of the sync signal, the digital filter sequencer is reset to 0. the filter is held in reset state until a rising edge of the sco senses sync high. thus, to perform a synchronization of devices, a sync pulse of a minimum of 2.5 iclk cycles in length can be applied, synchronous to the falling edge of sco. on the first rising edge of sco after sync goes logic high, the filter is taken out of reset, and the multiple parts gather input samples synchronously. following a sync , the digital filter needs time to settle before valid data can be read from the AD7763. the user knows there is valid data on the sdo line by checking the dvalid status bit (see d3 in the status bits listing) that is output with each conversion result. the time from the rising edge of sync until the dvalid bit is asserted is dependent on the filter configuration used. see the theory of operation section and the figures listed in table 6 for details on calculating the time until dvalid is asserted. sharing the serial bus the AD7763 functionality allows up to eight devices to share the same serial bus, sdo, depending on the decimation rate that is chosen. table 8 details the maximum number of devices that can share the same sdo line for each decimation rate (32, 64, 128, 256). table 8. maximum number of devices sharing sdo decimation rate sco (mhz) 32 64 128 256 maximum number of devices sharing sdo 40 20 2 n/a 4 2 8 4 8 8 the share pins sh[2:0] of all the devices sharing the serial bus must be programmed with the number of devices that are sharing the serial bus.
AD7763 rev. 0 | page 16 of 32 using the address pins adr[2:0], all devices that share the serial bus are assigned binary addresses from 000 to 111 (depending on the number of devices in the share scheme). the address assigned to each device must not have a value greater than the number of devices sharing the serial bus. thus, adr[2:0] sh[2:0]. this applies to all the devices that share the serial bus. note also that each of the devices in the share scheme must have a different individual address. for the device in the share scheme with an address of 000, the sdo line comes out of three-state on the first rising edge of sco after the drdy pulse and returns to three-state 5.5 ns before the 31st sco rising edge. for the next device sharing the serial bus, address 001, the sdo line comes out of three-state on the 33rd sco rising edge (that is, the first sco rising edge of the next conversion output cycle). thus, the sdo line goes into tri- state for one sco cycle in between data being clocked onto sdo by two different devices that share the sdo line. this means that a bus contention issue is avoided. this pattern of behavior continues for the rest of the devices sharing the serial bus. each AD7763 device sharing the serial bus outputs its own fso signal. figure 26 shows an example of four devices sharing the same serial bus. all the devices in the share chain shown in figure 26 operate in decimate 64 mode (selected by writing to control register 1address 0x001 ) and use a maximum sco signal of 40 mhz (see the clocking the AD7763 section). the share pins sh[2:0] of all the devices shown in figure 26 are set to 011, corresponding to the four devices that are in the share configuration. each AD7763 is hardwired with a different binary address ranging from 000 to 011, using the address pins adr[2:0]. the timing diagram for the share configuration shown in figure 26 is detailed in figure 4 . device a outputs its 32-bit conversion result on the sdo line during the first 32 sco cycles (as per the format shown in the reading data using the spi interface section). device b then outputs its conversion result during the next 32 sco cycles, and so on for device c and device d. note the way in which the sdo line is three- stated, separating data from each of the devices sharing the serial bus. the provision of two framing signals, drdy and fso , ensures that the AD7763 offers flexible data output framing options, which are further enhanced by the availability of the sdl output. the user can select the framing output that best suits the application. writing to the AD7763 figure 3 shows the AD7763 write operation. the serial writing operation is synchronous to the sco signal. the status of the frame sync input, fsi , is checked on the falling edge of the sco signal. if the fsi line is low, then the first data is latched in on the next sco falling edge. AD7763 (000) mclk device address 000 shared serial data output (sdo) device address 001 100 adr[2:0] fso fso a a sh[2:0] sh[2:0] mclk sdo drdy drdy AD7763 (001) mclk adr[2:0] fso fso b b sh[2:0] sdo device address 010 AD7763 (010) mclk adr[2:0] fso fso c c sh[2:0] sdo device address 011 AD7763 (011) mclk adr[2:0] fso fso d d sh[2:0] sdo 05476-013 figure 26. four AD7763 devices sharing the serial bus the active edge of the fsi signal should be set to occur at a position when the sco signal is high or low and which also allows setup and hold time from the sco falling edge to be met. the width of the fsi signal can be set to between 1 sco period and 32 sco periods wide. a second or subsequent fsi falling edge, which occurs before 32 sco periods have elapsed, is ignored. figure 3 also shows the format for the serial data written to the AD7763. a write operation requires 32 bits. the first 16 bits select the device and register address for which the data written is intended. the second 16 bits contain the data for the selected register. when using multiple devices that share the same serial bus, all fso and sdi pins can be tied together and each device written to individually by setting the appropriate address bits in the serial 32-bit word. the exception to this is when all devices can be written to at the same time by setting the all bit to logic high.
AD7763 rev. 0 | page 17 of 32 thus, if this bit is set to logic high, every device on the serial bus accepts the data written, regardless of the address bits. this feature is particularly attractive if, for example, four devices are being configured with the same user-defined filter. instead of having to download the filter configuration four times, only one write is required. see the downloading a user-defined filter section for further details. writing to AD7763 is allowed at any time, even while reading a conversion result. note that after writing to the devices, valid data is not output until after the settling time for the filter has elapsed. the dvalid status bit is asserted at this point to indicate that the filter has settled and that valid data is available at the output. reading status and other registers the AD7763 features a number of programmable registers. to read back the contents of these registers or the status register, the user must first write to the control register of the device, setting a bit corresponding to the register to be read. the next read operation then outputs the contents of the selected register instead of a conversion result. to ensure that the next read cycle contains the contents of the register that has been written to, the write operation to the register in question must be completed a minimum of 8 t sco before the falling edge of drdy , which indicates the start of the next read cycle. more information on the relevant bits in the control register is provided in the registers section.
AD7763 rev. 0 | page 18 of 32 reading data using the i 2 s interface AD7763 (000) mclk left channel right channel device address 000 device address 001 1 001 adr[2:0] fso ws a sh[2:0] i 2 s sh[2:0] mclk sco sdo sd sck 3-wire i 2 s interface 05476-026 AD7763 (001) mclk 1 sh[2:0] sdo b adr[2:0] i 2 s the AD7763 has the capability of operating using an i 2 s interface. the interface is functional only for the output of stereo data and does not apply to writing to control registers, programming coefficients for the digital filter, or the reading of any information contained in the AD7763 onboard registers. all of these operations must be undertaken using the normal serial interface. the i 2 s interface operates using two AD7763 devices. the pins shown in table 9 are used as the output pins for the sck (serial clock), sd (serial data), and ws (word select) signals for the i 2 s interface. table 9. spi pins i 2 s signals fso ws sdo sd sco sck figure 27. two AD7763 devices operating using the i 2 s interface to enable the i 2 s interface, the i 2 s pin is set to logic high. the share pins sh[2:0] of both AD7763 devices that use the i 2 s interface are set to 001. the address pins adr[2:0] of the two devices must also be set to 000 and 001, respectively. conversion results from device b, assigned address 001, are clocked out on the sd line when ws is logic high. the sd line goes into three-state on the falling edge of the 32nd sck after the falling edge of ws (left channel data) and also on the falling edge of the 32nd sck after the rising edge of ws (right channel data). this permits swapping of the sd bus between the left and right channel devices without contention. the ws and sck signals that are used for the interface can be taken from either AD7763 device. note that the device that is assigned address 000 is defined as the left channel, and its data is output on the sd line when ws is logic low. the ws and sck signals can be taken from the appropriate pins on either of the AD7763 devices using the i 2 s interface. the sd pins of both devices must be connected together, as shown in figure 27 . in decimate 32 mode the i 2 s interface is operational only when cdiv = 0 and scr = 1. the interface operates for all combinations of scr and cdiv in all other modes of decimation. data is clocked out on the sd line in accordance with figure 28 . because device a is assigned address 000, it is defined as the left channel. the 32-bit conversion result from the left channel is clocked out when ws is logic low, with the msb being clocked out first. each 32-bit result consists of 24 data bits in twos complement format, followed by eight status bits, as shown in the following bit map. d7 d6 d5 d4 d3 d2 d1 the drdy pulse still operates as in the normal serial spi-type interface, pulsing low immediately prior to the falling edge of ws but having no meaning in the i 2 s interface specification. d0 dvalid ovr ufilter lpwr filter_ok adr0 0 three- state st1 st2 d21 three- state d22 three- state three- state d23 d21 d22 right channel device b (word n ? 1) right channel device b (word n + 1) left channel device a (word n + 2) left channel device a (word n) d23 sck a (o) ws a (o) sd (o) st1 st2 05476-027 figure 28. timing diagram for i 2 s interface
AD7763 rev. 0 | page 19 of 32 clocking the AD7763 the AD7763 requires an external, low jitter clock source. this signal is applied to the mclk pin, and the mclkgnd pin is used to sense the ground from the clock source. an internal clock signal (iclk) is derived from the mclk input signal. the iclk controls the internal operations of the AD7763. the maximum iclk frequency is 20 mhz, but due to an internal clock divider, a range of mclk frequencies can be used. there are two ways to generate the iclk: iclk = mclk ( cdiv = 1) iclk = mclk /2 ( cdiv = 0) this option is pin selectable (pin 58). on power-up, the default is iclk = mclk/2 to ensure that the part can handle the maxi- mum mclk frequency of 40 mhz. for output data rates equal to those used in audio systems, a 12.288 mhz iclk frequency can be used. as shown in table 6 , output data rates of 192 khz, 96 khz, and 48 khz are achievable with this iclk frequency. as mentioned previously, this iclk frequency can be derived from different mclk frequencies. the mclk jitter requirements depend on a number of factors and are determined by 20 )db( )( 10 2 snr in rmsj f osr t = where: osr = oversampling ratio = odr f iclk . f in = maximum input frequency. snr (db) = target snr. example 1 this example is taken from table 6 , where: odr = 625 khz. f iclk = 20 mhz. f in (maximum) = 250 khz. snr = 108 db. ps6.3 10102502 32 63 )( = = rmsj t this is the maximum allowable clock jitter for a full-scale, 250 khz input tone with the given iclk and output data rate. example 2 following is a second example from table 6 , where: odr = 48 khz. f iclk = 12.288 mhz. f in (maximum) = 19.2 khz. snr = 120 db. ps133 10102.192 256 63 )( = = rmsj t the input amplitude also has an effect on these jitter figures. if, for example, the input level is 3 db below full scale, the allowable jitter is increased by a factor of 2, increasing the first example to 2.53 ps rms. this happens when the maximum slew rate is decreased by a reduction in amplitude. figure 29 and figure 30 illustrate this point, showing the maximum slew rate of a sine wave of the same frequency but with different amplitudes. 1.0 ?1.0 05476-014 0.5 0 ?0.5 figure 29. maximum slew rate of sine wave with amplitude of 2 v p-p 1.0 ?1.0 05476-015 0.5 0 ?0.5 figure 30. maximum slew rate of same frequency sine wave with amplitude of 1 v p-p
AD7763 rev. 0 | page 20 of 32 driving the AD7763 the AD7763 has an on-chip differential amplifier that operates with a supply voltage (av dd3 ) from 3.15 v to 5.25 v. for a 4.096 v reference, the supply voltage must be 5 v. to achieve the specified performance in normal mode, the differential amplifier should be configured as a first-order antialias filter, as shown in figure 31 . any additional filtering should be carried out in previous stages using low noise, high performance op amps, such as the ad8021 . suitable component values for the first-order filter are shown in table 10 . the values in table 10 yield a 10 db attenuation at the first alias point of 19 mhz. 0 5476-016 a1 r in r fb c fb r in r m r m c s r fb c fb v in ? a b v in + figure 31. differential amplifier configuration table 10. normal mode component values v ref r in r fb r m c s c fb 4.096 v 1 k 655 18 5.6 pf 33 pf figure 32 shows the signal conditioning that occurs using the circuit in figure 18 with a 2.5 v input signal biased around ground and having the component values and conditions in table 10 . the differential amplifier always biases the output signal to sit on the optimum common mode of v ref /2, in this case, 2.048 v. the signal is also scaled to give the maximum allowable voltage swing with this reference value. this is calculated as 80% of v ref ; that is, 0.8 4.096 v 3.275 v p-p on each input. to obtain maximum performance from the AD7763, it is advisable to drive the adc with differential signals. figure 33 shows how a bipolar, single-ended signal biased around ground can drive the AD7763 with the use of an external op amp, such as the ad8021 . with a 4.096 v reference, a 5 v supply must be provided to the reference buffer (av dd4 ). with a 2.5 v reference, a 3.3 v supply must be provided to av dd4 . 05476-017 + 2.5v 0v ? 2.5v + 2.5v 0v ? 2.5v +3.685v +2.048v +0.410v +3.685v +2.048v +0.410v a v in + v in ? b figure 32. differential amplifier signal conditioning 0 5476-018 a1 r in r fb c fb r in r m r m c s r fb c fb v in ? v in v in + ad8021 2r 2r r figure 33. single-ended-t o-differential conversion 05476-019 cs2 cpb2 ss4 sh4 cpa ss2 sh2 cs1 cpb1 ss3 sh3 ss1 sh1 analog modulator v in + figure 34. equivalent input circuit the AD7763 employs a double sampling front end, as shown in figure 34 . for simplicity, only the equivalent input circuit for v in + is shown. the equivalent input circuitry for v in ? is the same.
AD7763 rev. 0 | page 21 of 32 sampling switch ss1 and sampling switch ss3 are driven by iclk, whereas sampling switch ss2 and sampling switch ss4 are driven by iclk . when iclk is high, the analog input voltage is connected to cs1. on the falling edge of iclk, the ss1 and ss3 switches open, and the analog input is sampled on cs1. similarly, when iclk is low, the analog input voltage is connected to cs2. on the rising edge of iclk, the ss2 and ss4 switches open, and the analog input is sampled on cs2. capacitor cpa, capacitor cpb1, and capacitor cpb2 represent parasitic capacitances that include the junction capacitances associated with the mos switches. table 11. equivalent component values mode cs1 cs2 cpa cpb1/cpb2 normal 51 pf 51 pf 12 pf 20 pf low power 13 pf 13 pf 12 pf 5 pf using the AD7763 following is the recommended sequence for powering up and using the AD7763. 1. apply power. 2. start clock oscillator, applying mclk. 3. ta ke reset low for a minimum of 1 mclk cycle. 4. wait a minimum of 2 mclk cycles after reset has been released. 5. write to control register 2 to power up the adc and the differential amplifier, as required. 6. write to control register 1 to set up the output data rate. 7. in circumstances where multiple parts are being synchronized, a sync pulse must be applied to the parts; otherwise, no sync pulse is required. the following are conditions for applying the sync pulse: ? the issuing of a sync pulse to the part must not coincide with a write to the part. ? the sync pulse should be applied a minimum of 2.5 iclk cycles after the fsi signal for the previous write to the part has returned to logic high. ? ensure that the sync pulse is taken low for a minimum of 2.5 iclk cycles. data can now be read from the part using the default filter, offset, gain, and overrange threshold values. the conversion data read is not valid, however, until the settling time of the filter has passed. when this has occurred, the dvalid bit read is set, indicating that the data is indeed valid. the user can then download a user-defined filter, if required (see downloading a user-defined filter ). values for gain, offset, and overrange threshold registers can also be written or read at this stage. bias resistor selection the AD7763 requires a resistor to be connected between the r bias pin and agnd. the value for this resistor is dependent on the reference voltage being applied to the device. the resistor value should be selected to give a current of 25 a through the resistor to ground. for a 2.5 v reference voltage, the correct resistor value is 100 k ; for a 4.096 v reference voltage, the correct resistor value is 160 k .
AD7763 rev. 0 | page 22 of 32 decoupling and layout recommendations due to the high performance nature of the AD7763, correct decoupling and layout techniques are required to obtain the performan ce as stated within this data sheet. figure 35 shows a simplified connection diagram for the AD7763. ina+ ina? outa? outa+ vin+ vin? vref pin 14 pin 15 pin 4 pin 12 pin 6 pin 33 pin 24 pin 27 pin 44 pin 63 pin 41 r19 160k c64 33pf c7 100nf av dd3 pin 24 (vdif1) c54 100nf l6 dv dd pin 41 (dvdd) c58 100nf l8 av dd2 pin 4 (rhs) c48 100nf l1 pin 15 (vbias) c50 100nf l3 pin 14 (lhs) pin 27 c62 100nf l2 l9 av dd4 pin 12 (vbuf) c59 10nf l4 r38 10 av dd1 pin 5 (vmod1) c52 100nf l5 pin 33 (vmod2) c53 100nf l11 v drive pin 44 (vdrv1) c56 100nf l7 pin 63 (vdrv2) c57 100nf l12 v in a+ v in a? v out a? v out a+ decapa decapb v in + v in ? v ref + refgnd r bias dgnd dgnd dgnd dgnd dgnd dgnd dgnd 19 20 21 22 8 30 25 26 10 9 17 1 35 42 43 57 59 62 i 2 s scr sco sdo sdi sdl scp sh1 sh2 reset sync drdy mclk mclkgnd agnd1 agnd1 agnd2 agnd2 agnd2 agnd2 agnd2 agnd3 agnd3 agnd3 agnd3 agnd4 7 34 5 13 16 18 28 23 29 31 32 11 av dd2 av dd2 av dd2 av dd4 av dd1 av dd1 av dd3 av dd2 v drive v drive dv dd 14 15 4 12 6 33 24 27 44 63 41 AD7763bsv dgnd 53 61 60 58 55 54 50 49 46 45 40 37 36 38 3 2 56 52 51 48 47 39 u2 fsi fso sh0 cdiv 64 dgnd adr1 adr2 adr0 reset sync drdy mclk i 2 s scr sco sdo sdi sdl scp sh1 sh2 fsi fso cdiv sh0 adr1 adr2 adr0 05476-028 figure 35. simplified connection diagram
AD7763 rev. 0 | page 23 of 32 supply decoupling every supply pin must be connected to the appropriate supply via a ferrite bead and decoupled to the correct ground pin with a 100 nf, 0603 case size, x7r dielectric capacitor. there are two exceptions ? pin 12 (av dd4 ) must have a 10 resistor inserted between the pin and a 10 nf decoupling capacitor. ? pin 27 (av dd2 ) does not require a separate decoupling capacitor or a direct connection to the supply; instead, it is connected to pin 14 via an 8.2 nh inductor. the ferrite beads that are used to connect each supply pin to the appropriate power supply should have a characteristic impedance of 600 to 1 m at frequencies around 100 mhz, a dc impedance of 1 or less, and a rated current of 200 ma. additional decoupling there are two other decoupling pins on the AD7763: pin 8 (decapa) and pin 30 (decapb). pin 8 should be decoupled with a 100 nf capacitor, and pin 30 requires a 33 pf capacitor. reference voltage filtering a low noise reference source, such as the adr431 (2.5 v) or adr434 (4.096 v), is suitable for use with the AD7763. the reference voltage supplied to the AD7763 should be decoupled and filtered, as shown in figure 36 . the recommended scheme for the reference voltage supply is a 100 series resistor connected to a 100 f tantalum capacitor, followed by a series resistor of 10 , and finally, a 10 nf decoupling capacitor very close to the v ref pin. 05476-021 12v pin 10 vout 2 +vin 6 4 c15 10 f c9 100nf c10 100nf r30 100 r17 10 + c46 10nf c11 100 f + adr434 gnd u3 figure 36. reference connection differential amplifier components the correct components for use around the on-chip differential amplifier are shown in tabl e 10 . matching the components on both sides of the differential amplifier is important to minimize distortion of the signal applied to the amplifier. a tolerance of 0.1% or better is required for these components. symmetrical routing of the tracks on both sides of the differential amplifier also assists in achieving stated performance. exposed paddle the AD7763 64-lead tqfp_ep employs a 6 mm 6 mm exposed paddle (see figure 39 ). the paddle reduces the thermal resistance of the package by providing a path of low thermal resistance to the pcb and, in turn, increases the heat transfer efficiency from the AD7763 package. soldering the exposed paddle to the agnd plane of the pcb is fundamental in creating the conditions that allow the AD7763 package to perform to the highest specifications possible. layout considerations while using the correct components is essential to achieve optimum performance, the correct layout is just as important. the design tools section of the AD7763 product page on the analog devices website contains the gerber files for the AD7763 evaluation board. these files should be used as a reference when designing any system using the AD7763. the location and orientation of some of the components mentioned in previous sections are critical, and particular attention must be paid to the components that are located close to the AD7763. locating these components farther away from the devices can have a direct impact on the maximum performance achievable. the use of ground planes should also be carefully considered. to ensure that the return currents through the decoupling capacitors are flowing to the correct ground pin, the ground side of the capacitors should be as close as possible to the ground pin associated with that supply. a ground plane should not be relied upon as the sole return path for decoupling capacitors, because the return current path using ground planes is not easily predicted.
AD7763 rev. 0 | page 24 of 32 programmable fir filter as discussed in the theory of operation section, the third fir filter on the AD7763 can be programmed by the user. the default coefficients that are loaded on reset are shown in table 12 . this gives the frequency response shown in figure 37 . the frequencies shown in figure 37 scale directly with the output data rate. table 12. default filter coefficients # decimal value hex value # decimal value hex value 0 +53656736 332bca0 24 +700847 ab1af 1 +25142688 17fa5a0 25 ?70922 401150a 2 ?4497814 444a196 26 ?583959 408e917 3 ?11935847 4b62067 27 ?175934 402af3e 4 ?1313841 4140c31 28 +388667 5ee3b 5 +6976334 6a734e 29 +294000 47c70 6 +3268059 31dddb 30 ?183250 402cbd2 7 ?3794610 439e6b2 31 ?302597 4049e05 8 ?3747402 4392e4a 32 +16034 3ea2 9 +1509849 1709d9 33 +238315 3a2eb 10 +3428088 344ef8 34 +88266 158ca 11 +80255 1397f 35 ?143205 4022f65 12 ?2672124 428c5fc 36 ?128919 401f797 13 ?1056628 4101f74 37 +51794 ca52 14 +1741563 1a92fb 38 +121875 1dc13 15 +1502200 16ebf8 39 +16426 402a 16 ?835960 40cc178 40 ?90524 401619c 17 ?1528400 4175250 41 ?63899 400f99b 18 +93626 16dba 42 +45234 b0b2 19 +1269502 135efe 43 +114720 1c020 20 +411245 6466d 44 +102357 18fd5 21 ?864038 40d2f26 45 +52669 cdbd 22 ?664622 40a242e 46 +15559 3cc7 23 +434489 6a139 47 +1963 7ab the default filter should be sufficient for most applications. it is a standard brick wall filter with a symmetrical impulse response. the default filter has a length of 96 taps and is nonaliasing, with 120 db of attenuation at nyquist. this filter not only performs signal antialiasing but also suppresses out-of- band quantization noise produced by the analog-to-digital conversion process. any significant relaxation in the stop-band attenuation or transition bandwidth relative to the default filter can result in failure to meet the snr specifications. to create a user-defined filter, note the following: ? the filter must be even, symmetrical fir. ? the coefficients are 27 bits in length. all coefficients are in sign-and-magnitude format. the sign bit coded as positive = 0 is followed by 26 magnitude bits. ? the filter length must be between 12 taps and 96 taps in steps of 12. ? because the filter is symmetrical, the number of coefficients that must be downloaded is half the filter length. the default filter coefficients are an example of this, with only 48 coefficients listed for a 96-tap filter. ? coefficients are written from the center of impulse response (adjacent to the point of symmetry) outward. ? the coefficients are scaled so that the in-band gain of the filter is equal to 134217726, with the coefficients rounded to the nearest integer. for a low-pass filter, this is the equivalent of having the coefficients sum arithmetically (including sign) to +67108863 (0x3ffffff) positive value over the half-impulse-response coefficient set (maximum 48 coefficients). any deviation from this results in the introduction of a gain error. ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 100 400 500 300 200 600 frequency (khz) amplitude (db) 0 05476-022 ?0.1db frequency = 251khz pass-band ripple = 0.05db stop band = 312.5khz ?3db frequency = 256khz figure 37. default filter frequency response (625 khz odr) to download a user-defined filter, see the downloading a user- defined filter section.
AD7763 rev. 0 | page 25 of 32 downloading a user-defined filter as discussed in the programmable fir filter section, each of the filter coefficients is 27 bits in length: one sign bit and 26 magni- tude bits. to download coefficients for a user-specific fir filter, a 32-bit word is written to the AD7763 for each coefficient. d31 d30 d29 d28 d27 d26 d[25:0] all adr2 adr1 adr0 0 sign magnitude when a user writes coefficients to one device, the address of that particular device (as assigned by the adr[2:0] pins) must be specified in the bits labeled adr[2:0]. in a configuration where more than one device shares the same sdi line, setting the all bit to logic high and leaving address bits adr[2:0] logic low enables the user to write each coefficient to all devices simultaneously. to ensure that a filter is downloaded correctly, a checksum must be generated and downloaded following the download of the final coefficient. the checksum is a 16-bit word generated by splitting each 32-bit word into 4 bytes and summing all bytes from all coefficients up to a maximum of 192 bytes (maximum number of coefficients = 48 bytes 4 bytes written for each coefficient). the checksum is written to the device in the form of a 32-bit word in the following format: d31 d30 d29 d28 d[27:16] d[15:0] all adr2 adr1 adr0 0 checksum note that when writing the checksum, the addressing requirements are as before, and bit 27 to bit 16 are all set to 0. the same checksum is generated internally in the AD7763 and compared with the checksum downloaded. the dl_ok bit in the status register is set if these two checksums agree. to download a user-defined filter: 1. write to control register 1, setting the dl filt bit. the correct filter length bits flen[3:0] correspond to the length of the filter about to be downloaded (see tabl e 13 ) and the correct decimation rate. 2. write the 32-bit word (as per format specified). the first coefficient to be written must be the one adjacent to the point of filter symmetry. 3. repeat step 2 for each coefficient. 4. implement the checksum write as per the specified format. 5. use the following methods to verify that the filter coefficients have been downloaded correctly: ? read the status register, checking the dl_ok bit. ? start reading data and observe the status of the dl_ok bit. note that because the user coefficients are stored in ram, they are cleared after a reset operation or a loss of power. table 13. filter length values flen[3:0] number of coefficients filter length 0000 default default 0001 6 12 0011 12 24 0101 18 36 0111 24 48 1001 30 60 1011 36 72 1101 42 84 1111 48 96
AD7763 rev. 0 | page 26 of 32 example filter download the following is an example of downloading a short, user-defined filter with 24 taps. the frequency response is shown in figure 38 . 10 ?80 0 600 frequency (khz) amplitude (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 100 200 300 400 500 05476-023 figure 38. 24-tap fir frequency response the coefficients for the filter in table 14 are shown from the center of symmetry outward; that is, coefficient 1 is the coefficient at the center of symmetry. the raw coefficients were generated using a commercial filter design tool and scaled appropriately so their sum equals 67108863 (0x3ff ffff). table 14. 24-tap fir coefficients coefficient raw scaled 1 +0.365481974 +53188232 2 +0.201339905 +29300796 3 +0.009636604 +1402406 4 ?0.075708848 ?11017834 5 ?0.042856209 ?6236822 6 +0.019944246 +2902466 7 +0.036437914 +5302774 8 +0.007592007 +1104856 9 ?0.021556583 ?3137108 10 ?0.024888355 ?3621978 11 ?0.012379538 ?1801582 12 ?0.001905756 ?277343 table 15 shows the 32-bit word (as per the format shown in the downloading a user-defined filter section) in hexadecimal for each of the coefficients that must be written to the AD7763 to realize this filter. the table is also split into the bytes that are all summed to produce the checksum. the checksum generated from these coefficients is 0x0e6b. table 15. filter hex values 1 32-bit word written to download coefficient coefficient byte 1 byte 2 byte 3 byte 4 1 03 2b 96 88 2 01 bf 18 3c 3 00 15 66 26 4 04 a8 1e 6a 5 04 5f 2a 96 6 00 2c 49 c2 7 00 50 e9 f6 8 00 10 db d8 9 04 2f de 54 10 04 37 44 5a 11 04 1b 7d 6e 12 04 04 3b 5f 1 all values of words listed are with reference to writing to one device only (all = 0) with address 000 (as assigned to the device us ing the adr[2:0] pins). table 16 lists in hexadecimal format the sequence of 32-bit words the user writes to the AD7763 to set up the adc and download this filter, assuming selection of an output data rate of 625 khz. table 16. word 1 description 0x0001807a address of control register 1. control register data. dl filter, set filter length = 24, set output data rate = 625 khz. 0x032b9688 first coefficient. 0x01bf183c second coefficient. other coefficients. 0x04043b5f twelfth (final) coefficient. 0x00000e6b checksum. wait (0.5 t iclk number of unused coefficients) for AD7763 to fill remaining unused coefficients with 0s. 0x0001087a address of control register. control register data. set read status and maintain filter length and decimation settings. read contents of status register. check bit 7 (dl_ok) to determine that the filter downloaded correctly. 1 all values of words listed are with reference to writing to one device only (all = 0) with address 000 (as assigned to the device us ing the adr[2:0] pins).
AD7763 rev. 0 | page 27 of 32 registers the AD7763 has a number of user-programmable registers. the control registers are used to set the decimation rate, the filter c onfiguration, the low power option, and the control of the differential amplifier. there are also digital gain, offset, and overrange threshold registers. writing to these registers involves writing the register address first, followed by a 16-bit data-word. register addresses, det ails of individual bits, and default values are shown here. control register 1address 0x001 default value 0x001a msb lsb dl filt rd ovr rd gain rd off rd stat 0 sync flen3 flen2 flen1 flen0 byp f3 1 dec2 dec1 dec0 table 17. bit mnemonic comment 15 dl filt 1 download filter. before downloading a user-defined filter, th is bit must be set. the filter length bits must also be set at this time. the write operations that follow are inte rpreted as the user coefficien ts for the fir filter until all the coefficients and the checksum have been written. 14 rd ovr 1 , 2 read overrange. if this bit is set, the next read operat ion outputs the contents of th e overrange threshold register instead of a conversion result. 13 rd gain 1 , 2 read gain. if this bit is set, the next read operati on outputs the contents of the digital gain register. 12 rd off , 1 2 read offset. if this bit is set, the next read operati on outputs the contents of the digital offset register. 11 rd stat 1 , 2 read status. if this bit is set, the next read ope ration outputs the contents of the status register. 10 0 0 must be written to this bit. 9 sync 1 synchronize. setting this bit initiates an internal sy nchronization routine. setting this bit simultaneously on multiple devices synchronizes all filters. 8 to 5 flen[3:0] filter length bits. these bits must be set when the dl filt bit is set and before a user-defined filter is dow nloaded. 4 byp f3 bypass filter 3. if this bit is a 0, filter 3 (programmable fir) is bypassed. 3 1 1 must be written to this bit. 2 to 0 dec[2:0] decimation rate. these bits set the decimation rate of filt er 2. writing a value of 0, 1, or 2 corresponds to 4 decimation. a value of 3 corresponds to 8 decimation; a value of 4 corresponds to 16; and the maximum value of 5 corresponds to 32 decimation. 1 bit 15 to bit 9 are all self-clearing bits. 2 only one of these bits can be set in any write operation, because they all determine the contents of the next operation. control register 2address 0x002 default value 0x009b msb lsb 0 0 0 0 0 0 0 0 0 0 0 0 pd lpwr 1 d1pd table 18. bit mnemonic comment 3 pd power down. setting this bit powers down th e AD7763, reducing the power consumption to 6.35 mw. 2 lpwr low power. if this bit is set, the AD7763 operates in a low power mode. the power consumption is reduced for a 3 db reduction in noise performance. 1 1 1 must be written to this bit. 0 d1pd differential amplifier power down. setting this bit powers down the on-chip differential amplifier.
AD7763 rev. 0 | page 28 of 32 status register (read only) msb lsb part 1 part 0 die 2 die 1 die 0 0 lpwr ovr dl_ok filter_ok ufilter byp f3 1 dec2 dec1 dec0 table 19. bit mnemonic comment 15,14 part[1:0] part number. these bits are constant for the AD7763. 13 to 11 die[2:0] die number. these bits reflect the current ad 7763 die number for identification purposes within a system. 10 0 0 must be written to this bit. 9 lpwr low power. if the AD7763 is operating in low power mode, this bit is set to 1. 8 ovr if the current analog input exceeds the cu rrent overrange threshol d, this bit is set. 7 dl_ok when downloading a user filter to the AD7763, a checksum is generated. this checksum is compared to the one downloaded following the coefficients. if these checksums agree, this bit is set. 6 filter_ok when a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. this generated checksum is compared to th e one downloaded. if they match, this bit is set. 5 ufilter if a user-defined filter is in use, this bit is set. 4 byp f3 bypass filter 3. if filter 3 is bypassed by setting the relevant bit in control register 1, this bit is also set. 3 1 1 must be written to this bit. 2 to 0 dec[2:0] decimation rate. these bits corr espond to the bits set in control register 1. offset registeraddress 0x003 non bit-mapped, default value 0x0000 the offset register uses twos complement notation and is scaled so that 0x7fff (maximum positive value) and 0x8000 (maximum negative value) correspond to an offset of +0.390625% and ?0.390625%, respectively. offset correction is applied after any gain correction. using the default gain value of 1.25 and assuming a reference voltage of 4.096 v, the offset correction range is approximately 25 mv. gain registeraddress 0x004 non bit-mapped, default value 0xa000 the gain register is scaled so that 0x8000 corresponds to a gain of 1.0. the default value of this register is 1.25 (0xa000). this gives a full-scale digital output when the input is at 80% of v ref . this ties in with the maximum analog input range of 80% of v ref p-p. overrange registeraddress 0x005 non bit-mapped, default value 0xcccc the overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum propagation delay. this is prior to any gain scaling or offset adjustment. the default value is 0xcccc, which corresponds to 80% of v ref (the maximum permitted analog input voltage). assuming v ref = 4.096 v, the bit is then set when the input voltage exceeds approximately 6.55 v p-p differential. note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of v ref for more than 4 consecutive samples at the modulator rate.
AD7763 rev. 0 | page 29 of 32 outline dimensions compliant to jedec standards ms-026-acd-hd 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 49 64 1 17 16 32 33 48 1.20 max 0.75 0.60 0.45 view a top view (pins down) pin 1 49 64 17 1 16 32 33 48 0.50 bsc lead pitch 0.38 0.32 0.22 bottom view (pins up) 6.00 bsc sq exposed pad 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 figure 39. 64-lead thin quad flat package, exposed pad [tqfp_ep] (sv-64-2) dimensions shown in millimeters ordering guide model temperature range package description package option AD7763bsvz 1 ?40c to +85c 64-lead thin quad flat package, exposed pad (tqfp_ep) sv-64-2 AD7763bsvz-reel 1 ?40c to +85c 64-lead thin quad flat package, exposed pad (tqfp_ep) sv-64-2 eval-AD7763eb evaluation board 1 z = pb-free part.
AD7763 rev. 0 | page 30 of 32 notes
AD7763 rev. 0 | page 31 of 32 notes
AD7763 rev. 0 | page 32 of 32 notes ? 2005 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05476-0-10/05(0)

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